1. Field of the Invention
The present invention relates to the simulation of logic circuits by means of a standardized language, such as VHDL or Verilog.
2. Discussion of the Related Art
VHDL, for example, is a high level language enabling a designer to define a complete logic circuit by a functional description. The description produced by the designer can be synthesizable or simulatable.
The synthesizable description is meant, through an appropriate software processing, to synthesize the circuit, that is, generate a definition of the elements that constitute the circuit (a netlist) which is directly exploitable by placement and routing tools for fabricating the corresponding integrated circuit.
During a synthesis step, the synthesizable description is decomposed into elementary logic functions implementable by elementary logic gates.
A simulatable description is meant to be processed by a logic simulator for generating, in particular, timing diagrams more or less accurately representing the logic evolution of the signals which will exist in a real circuit, this in order to check the proper operation of the circuit before effectively manufacturing it.
A simulatable description could include a synthesizable description only. The simulation would then provide the purely logic behavior of the circuit, which is however insufficient since the real elements of the circuit introduce signal delays which are not taken into account by a synthesizable description. These delays are likely to cause malfunctions of the real circuit whereas the pure logic behavior of the circuit is correct.
To detect these malfunctions, a simulatable description includes additional parameters to take delays into account.
A preliminary step in a simulation generally consists in converting a synthesizable description into a simulatable description by an automated processing. The synthesizable description is decomposed into elementary logic functions which are finally replaced with predefined models corresponding to elementary logic gates.
FIG. 1 schematically shows a general model of a logic gate. The model includes, in the general case, several inputs IN1 to INn and one output OUT connected to a capacitive load C. In this model, a logic table supplies the logic state of output OUT according to the logic states of the inputs (including output OUT itself for a flip-flop). Further, a description of the behavior in time defines the reaction delay of the output according to each input. More specifically, the model stores at least one delay tp per input and, if a change of state of one of inputs INi should cause a transition on output OUT, the model generates this transition after the delay tpi associated with input INi.
The simulated signals are purely logic, that is, they only take states xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d.
Hereafter, for clarity, a single-input model is considered, more specifically an inverter model. The following lines of VHDL partially represent an example of a simplified inverter model:
The lines between xe2x80x9centity IV isxe2x80x9d and xe2x80x9cend IVxe2x80x9d define the input IN and the output OUT of the inverter, as well as the delay parameters. There are here two delay parameters. Parameter IN_fall_OUT_rise defines the delay of a rising edge of signal OUT with respect to a falling edge of signal IN, and parameter IN_rise_OUT_fall defines the delay of a falling edge of output OUT with respect to a rising edge of input IN. Two parameters are thus available for a single input, which provides a good accuracy of the results of the simulation.
The lines between xe2x80x9cArchitecture naive Of IV Isxe2x80x9d and xe2x80x9cEnd naivexe2x80x9d define the behavior of the inverter. Procedure xe2x80x9cProcess(IN)xe2x80x9d is executed once for each change of state of input signal IN. Thus, as soon as signal IN changes state, it is checked whether its state is xe2x80x9c1xe2x80x9d. If such is the case, a variable xe2x80x9cdelayxe2x80x9d is assigned with parameter IN_rise_OUT_fall. Otherwise, variable xe2x80x9cdelayxe2x80x9d is assigned with the second parameter IN_fall_OUT_rise. Then, output signal OUT receives the complement of input signal IN when the time contained in variable xe2x80x9cdelayxe2x80x9d expires.
The numerical values of the parameters indicated in the above example are default values depending on the used technology. One of the problems in simulation lies in the refining of the default parameters according to the real structure of the entire circuit.
FIG. 2 illustrates the calculation of a delay in the case of an inverter. Signals INR and OUTR correspond to the real input and output signals of the inverter. Signals INS and OUTS are simulated signals associated with real signals INR and OUTR.
At time t0, signal INR starts a rising transition shown, for simplicity, by a straight segment Isl. The rising transition of signal INR causes a reaction of the inverter after a certain delay which depends on the technology used and on the slope Isl of the transition of input signal INR. Thus, real output signal OUTR only starts a falling transition at a delayed time t2. The slope Osl of this falling transition depends on the capacitive load C of the line to which the inverter output is connected, but also on slope Isl of the transition of input signal INR.
Simulated signals INS and OUTS take only one or the other of logic states xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, and therefore cannot reflect the slopes of the transitions. Thus, it is assumed that the state of simulated input signal INS switches from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d at a time t1 when the rising transition of real signal INR reaches a predetermined threshold. Similarly, it is assumed that the state of simulated output signal OUTS switches from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d at a time t3 when the falling transition of real signal OUTR reaches a predetermined threshold. In the example shown, the switching thresholds correspond to 50% of the high logic level, for both the rising transitions and the falling transitions of the real signals. It is also usual to use a 40% threshold for rising transitions and a 60% threshold for falling transitions.
Delay tp is the duration separating the times t1 and t3 where the transitions of real signals INR and OUTR cross the switching thresholds, that is, the duration which separates the transitions of simulated signals INS and OUTS.
As mentioned above, slope Osl of the output transition is a function of slope Isl of the input transition and of the capacitive load C to be controlled by the gate""s output. As appears in FIG. 2, delay tp depends on slope Osl of the output transition and is thus also a function of slope Isl of the input transition and of load C. To summarize, tp=fd(C, Isl) and Osl=fs(C, Isl), where fd and fs are the two above-mentioned functions.
In the general case of a model with several inputs:
tpi=fdi(C, Isli)
and
Osli=fsi(C, Isli),
where index i designates the input to which the delay and slope values are associated.
Currently, to perform an accurate simulation, the layout of the final circuit is first designed, which enables a relatively accurate calculation of the capacitive loads of the various lines interconnecting the logic elements. Further, the sizes of the transistors and the technology used determine the capacitances of the inputs of the logic elements, which add to the line capacitances.
When the capacitive loads have been calculated in this manner, a so-called back-annotation of the models is performed, which consists in replacing the default delays by values calculated before the simulation from the capacitive loads found.
In the general case, the output of a first model A with several inputs is connected to an input of a second model B. The delay tpB associated with the input of model B is normally calculated from the slope of the input signal of model B, that is, from slope Osli of the output signal of model A. Now, this output signal depends on function fsi associated with that of the inputs (i) of model A which switches.
Thus, a same input of a model may receive signals with different slopes, whereas the corresponding delay calculated in the back-annotation procedure can only take a single one of these slopes into account.
To ensure the reliability of the simulation result, the delays are calculated in the worst case situation, that is, for the smallest slopes of the input signals. This solution is not optimal since it is likely to invalidate many circuit topologies which would operate properly in reality.
FIG. 3 illustrates an example of a circuit which would be invalidated by a simulation using the conventional back-annotation procedure. This circuit includes a flip-flop 10, the output Q of which is supplied to a flip-flop 12 via a succession of gates 14 with several inputs. Flip-flops 10 and 12 are enabled by a same clock signal CK.
For such a circuit to operate properly, a transition of output Q of flip-flop 10 should be transmitted to input D of flip-flop 12 before a next transition of clock signal CK, that is, normally before the expiry of a clock period. Otherwise, the transition is lost. Thus, the sum of the delays of gates 14 must be smaller than a clock period.
In practice, the designer will attempt to limit the delays in the critical paths, that is, the paths of the type connecting the input of flip-flop 12 to the output of flip-flop 10, by reducing as much as possible the capacitive loads in these critical paths. Conversely, the lines connected to the inputs of gates 14 which are not in a critical path may, without it being impairing, have a high capacitive load, as shown by capacitors 16.
By using the conventional back-annotation procedure, the delays of gates 14 will be calculated in the worst case situation, that is, according to the slopes of the signals on the inputs outside the critical path. Thus, the whole task of the designer in optimizing the critical path is ignored during the simulation which thereby may invalidate the circuit whereas this circuit operates perfectly in reality.
The back-annotation procedure also has drawbacks in the estimation of the power consumed by the real circuit. Indeed, a CMOS circuit only consumes power during transitions, and the power consumed increases as the slope of the transitions decreases. Thus, in the worst case situation where it is assumed that all slopes are at their lowest value, the estimated power is likely to be much higher than the real power.
An object of the present invention is to provide a logic circuit simulation method which provides better accuracy in the simulation and power estimation results.
These and other objects are achieved by a method of logic simulation, in which a signal is switched between two logic states to simulate a transition of a real signal. The method includes a step of inserting between the two logic states of the signal an intermediate state during a time interval indicative of the slope of the transition of the real signal.
According to an embodiment of the present invention, a model receiving at least one input signal and providing an output signal after a delay with respect to the input signal is used. The method then includes the steps of measuring a first time interval during which the input signal is at the intermediate state and determining the delay according to this time interval, the start time of the delay, and slope information of the output signal; determining, according to the end of the delay and the output signal slope information, the start time of a transition of the output signal; and, at the beginning of the transition of the output signal, assigning to the output signal the intermediate state during a second time interval indicative of the slope of the output signal.
According to an embodiment of the present invention, the output signal slope information is the second time interval.
According to an embodiment of the present invention, the start time of the delay is considered as the point where a real transition corresponding to the input signal reaches a predetermined switching threshold between the low and high levels.
According to an embodiment of the present invention, the end of the delay is considered as the point where a real transition corresponding to the output signal reaches a predetermined switching threshold between the low and high levels.
According to an embodiment of the present invention, the first and second time intervals are equal to a predetermined fraction of the respective durations of the real transitions.
According to an embodiment of the present invention, the first and second time intervals are substantially equal to the time required for the respective real transitions to vary by a MOS transistor threshold voltage.
According to an embodiment of the present invention, the method is implemented by means of a standardized language also used for synthesizing the logic gate, the intermediate state being the standardized xe2x80x9cdon""t carexe2x80x9d state.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments, in connection with the accompanying drawings.